Side Menu
Accelonix EMEA | Testway










TestWay’s electrical DfT analyzer enables designers to validate designs at the schematic capture stage, to ensure that adequate measures have been included to comply with the manufacturers test requirements. The ability to verify that PCB designs have been developed with adequate Design-for-Test in mind, is key in determining the most effective test strategies and accurately calculating fault coverage, which is crucial in improving competitive advantage, lowering cost and ensuring product quality.

The TestWay open architecture is based on a testability framework that interfaces to a variety of plug-in modules that provides both import and export opportunities, as shown below:

Solicitar Presupuesto

TestWay reads the board level netlist (schematic or layout) and model libraries. It then performs a basic topological analysis and symbolic simulation, and checks each rule, using both topological and accessibility data. TestWay will then produce a testability report, written in a natural language that can be used by design and test engineers to validate that specific DfT criteria have been implemented.

Key product benefits

Design rules checking

Verify that specific design rules have been adhered to prior to committing to PCB layout. Prevent costly design errors at the earliest possible opportunity.

DfT rules checking

Verify that DfT requirements are adhered to in order to maximize test coverage aligned to the PCB manufacturers test flow. Provide In-Circuit test rules to insure partitioning and initialization pin controllability; Boundary-Scan test rules to check Boundary Scan path integrity (JTAG), test bus control and correct termination etc.

Custom rules checking

Define and implement your own Customer’s rules rules that reflect your company or customer’s specific testability requirements.

Test point saving

Identify nets not requiring physical test access and only place test points where absolutely necessary. TestWay balances the different test approaches provided by AOI, AXI, BST, FT, FPT, ICT etc, and optimizes the number of mandatory test accesses, resulting in fewer test probes and significantly reduces test fixturing costs due to less complex fixtures.

Test coverage estimation

Maximize test and inspection coverage by estimating coverage aligned to test strategy. Perform ‘what-if’ analysis to select optimal test strategy to achieve maximum coverage based on historical DPMO data and eliminate redundant test steps. The resultant test coverage analysis can be viewed either graphically within the viewer, or as a test coverage report.

Test coverage measurement

Determine real test efficiency against theoretical coverage and identify areas for improvement. By reading real test programs or coverage reports, TestWay controls real test efficiency against estimated coverage, identifying uncovered areas and any redundant tests.

Functional test coverage

Manage functional test as part of the overall test strategy, produce accurate coverage reports that assists the diagnosis of faulty boards in production and repair centers.

Test Interface

TestWay generates input files for the following Boundary-Scan, In-Circuit & Flying-Probe testers including board description and device models.

Board visualization

Visualize test coverage and customer specific attributes in schematic, layout and netlist navigation views. This New-Generation Viewer also provides unique digitization feature that creates schematic view from PDF.

Advanced reporting

Produce comprehensive reports in a variety of formats that highlight predicted production yield, test coverage by component type, predict placement time, etc.

Cost modeling

Predict test execution times, total engineering time and calculate hardware costs such as; test fixture, power supply, spring probes, wiring and vector-less sensors etc.